A system in package based on a piezoelectric micromachined ultrasonic transducer matrix for ranging applications

This paper proposes a system in package (SiP) for ultrasonic ranging composed of a 4 × 8 matrix of piezoelectric micromachined ultrasonic transducers (PMUT) and an interface integrated circuit (IC). The PMUT matrix is fabricated using the PiezoMUMPS process and the IC is implemented in the AMS 0.35 µm technology. Simulation results for the PMUT are compared to the measurement results, and an equivalent circuit has been derived to allow a better approximation of the load of the PMUT on the IC. The control circuit is composed of a high-voltage pulser to drive the PMUT for transmission and of a transimpedance amplifier to amplify the received echo. The working frequency of the system is 1.5 MHz

Silicon carbide micro-electromechanical resonators for highly integrated frequency synthesizers

A low temperature (<300ºC), low-stress micro-electromechanical systems (MEMS) fabrication process based on a mechanically superior silicon carbide structural layer is outlined. The process is designed for low-cost film deposition and CMOS post-integration, stemming from chemical and thermal compatibility. MEMS beam resonators and arrays are fabricated, and have higher power handling capabilities and operating frequencies, compared to those of similar polysilicon-based resonators. A tuning method based on integrated heaters is introduced, yielding constant insertion loss tuning and wide tuning ranges. Quality factors of up to 1493 and resonant frequencies of up to 26.2 MHz are measured. A MEMS beam resonator model that accounts for electrostatic and mechanical non-linearities, and that may be used in circuit simulators is proposed. The model captures non-linear effects such as resonant frequency shifting and Duffing behaviour. It offers valuable insights into the trade-offs involved in the design optimization of MEMS resonator-based oscillators. Such oscillators are designed using an integrated high gain-bandwidth trans-impedance amplifier (TIA) combined with a resonator. The TIA employs automatic gain control to mitigate the inherent low power handling capabilities and the non-linearities of the MEMS device, thus minimizing their effect on phase noise. A highly integrated 1.7-2.0 GHz digitally programmable fractional-N frequency synthesizer using a MEMS resonator-based oscillator as its frequency reference is presented. Due to the dimensions of the MEMS device (e.g. 25 um by 114 um), the entire system with a total area of 6.25 mm2 can be housed in a small standard chip package. This considerably reduces the form factor and cost of the system, compared to using an external crystal as a reference. The synthesizer has a fine frequency resolution (~11 Hz) in order to allow for high output frequency stability when used with an appropriate control loop. A fully integUne technologie de fabrication de microsystèmes électromécaniques (MEMS) à basse température (<300ºC) incorporant une couche structurelle de carbure de silicium à faible contrainte est décrite. Une implémentation peu dispendieuse et une intégration avec les procédés CMOS qui découle d'une compatibilité chimique et thermique sont possibles. Des micro-résonateurs en forme de poutre et des résonateurs couplés sont fabriqués. Ceux-ci transigent des puissances plus grandes et ont des fréquences de résonance plus élevées comparativement à des structures en poly-silicium. Une méthode pour ajuster la fréquence de résonance avec un élément chauffant intégré est introduite et permet une perte d'insertion constante et une vaste gamme d'ajustement. Des facteurs de qualité allant jusqu'à 1493 et des fréquences de résonance allant jusqu'à 26.2 MHz sont mesurés. Un modèle est conçu pour tenir compte des non-linéarités électrostatiques et mécaniques du résonateur et peut être utilisé au sein d'un simulateur de circuits. Il capture les effets non-linéaires tels l'ajustement de la fréquence de résonance et le comportement de Duffing. Les compromis lors de la conception d'oscillateurs basés sur des résonateurs peuvent être discernés avec ce modèle. Ces oscillateurs sont conçus à l'aide d'un amplificateur de transimpédance qui emploie un contrôle du gain automatique pour réduire l'impact des non-linéarités du résonateur et permet la réduction du bruit de phase. Un synthétiseur de fréquences à division fractionnelle hautement intégré est présenté. Celui-ci couvre la bande de 1.7 GHz à 2.0 GHz et incorpore un oscillateur basé sur un résonateur MEMS pour sa référence de fréquence. Les petites dimensions du résonateur (ex: 25 um par 114 um) confèrent au système une superficie totale de 6.25 mm2 et permettent de le placer dans un boitier. La superficie et le coût du système sont réduits comparativement à u

Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22&nbsp;nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26&nbsp;dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4&nbsp;dB to 3.9&nbsp;dB, S11&lt;&minus;10&nbsp;dB and an IIP3 from &minus;7.5&nbsp;dBm to &minus;10.5&nbsp;dBm, over the RF operating band from 0.4&nbsp;GHz to 12&nbsp;GHz. The stacked receiver achieves a conversion-gain from 34.5&nbsp;dB to 36&nbsp;dB, a NFDSB from 4.6&nbsp;dB to 6.2&nbsp;dB, S11&lt;&minus;10&nbsp;dB, and an IIP3 from &minus;21&nbsp;dBm to &minus;17.5&nbsp;dBm, over the RF operating band from 2.2&nbsp;GHz to 3.2&nbsp;GHz. The cascaded receiver consumes 11 m from a 1&nbsp;V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2&nbsp;V supply voltage

A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications

This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 nm CMOS technology and occupies an active area of 0.025 mm2. It achieves a wideband input matching of less than −10 dB from 0.8 GHz to 3.4 GHz. A conversion-gain of 39.5 dB, IIP3 of −28 dBm and a double-sideband (DSB) NF of 5.6 dB is simulated at a local-oscillator (LO) frequency of 2.4 GHz and an intermediate frequency (IF) of 10 MHz, while consuming 1.92 mA from a 1.2 V supply

A Comparison of Off-Chip Differential and LC Input Matching Baluns in a Wideband and Low-Power RF-to-BB Current-Reuse Receiver Front-End

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a 1/f noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC 130&nbsp;nm CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54 mm2. From 1 to 1.7&nbsp;GHz, it achieves a conversion gain of 41.5&nbsp;dB, a double-sideband (DSB) NF of 6.5&nbsp;dB, S11&lt;&minus;10&nbsp;dB, and an IIP3 of &minus;28.2&nbsp;dBm, while the local-oscillator (LO) frequency is at 1.3&nbsp;GHz. CRR2 occupies an active area of 0.025 mm2. From 0.2 to 1 GHz, it achieves an average conversion gain of 37 dB, an average DSB NF of 8 dB, and an IIP3 of &minus;21.5&nbsp;dBm while the LO frequency is at 0.7&nbsp;GHz. Both CRR1 and CRR2 consume 1.66&nbsp;mA from a 1.2&nbsp;V supply voltage

A Comparison of Off-Chip Differential and LC Input Matching Baluns in a Wideband and Low-Power RF-to-BB Current-Reuse Receiver Front-End

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a 1/f noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC 130 nm CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54 mm2. From 1 to 1.7 GHz, it achieves a conversion gain of 41.5 dB, a double-sideband (DSB) NF of 6.5 dB, S11−10 dB, and an IIP3 of −28.2 dBm, while the local-oscillator (LO) frequency is at 1.3 GHz. CRR2 occupies an active area of 0.025 mm2. From 0.2 to 1 GHz, it achieves an average conversion gain of 37 dB, an average DSB NF of 8 dB, and an IIP3 of −21.5 dBm while the LO frequency is at 0.7 GHz. Both CRR1 and CRR2 consume 1.66 mA from a 1.2 V supply voltage

OSCAR: An Optimized Scheduling Cell Allocation Algorithm for Convergecast in IEEE 802.15.4e TSCH Networks

Today’s wireless sensor networks expect to receive increasingly more data from different sources. The Time Slotted Channel Hopping (TSCH) protocol defined in the IEEE 802.15.4-2015 version of the IEEE 802.15.4 standard plays a crucial role in reducing latency and minimizing energy consumption. In the case of convergecast traffic, nodes close to the root have consistently heavy traffic and suffer from severe network congestion problems. In this paper, we propose OSCAR, an novel autonomous scheduling TSCH cell allocation algorithm based on Orchestra. This new design differs from Orchestra by allocating slots according to the location of the node relative to the root. The goal of this algorithm is to allocate slots to nodes according to their needs. This algorithm manages the number of timeslots allocated to each node using the value of the rank described by the RPL routing protocol. The goal is that the closer the node is to the root, the more slots it gets in order to maximize the transmission opportunities. To avoid overconsumption, OSCAR sets up a mechanism to adjust the radio duty cycle of each node by reducing the slots allocated to inactive nodes regardless of their position in the network. We implement OSCAR on Contiki-ng and evaluate its performance by both simulations and experimentation. The performance assessment of OSCAR shows that it outperforms Orchestra on the average latency and reliability, without significantly increasing the average duty cycle, especially when the traffic load is high

Ionization Gas Sensor Using Suspended Carbon Nanotube Beams

An ionization sensor based on suspended carbon nanotubes (CNTs) was presented. A suspended CNT beam was fabricated by a low-temperature surface micromachining process using SU8 photoresist as the sacrificial layer. Application of a bias to the CNT beam generated very high non-linear electric fields near the tips of individual CNTs sufficient to ionize target gas molecules and initiate a breakdown current. The sensing mechanism of the CNT ionization sensor was discussed. The sensor response was tested in air, nitrogen, argon, and helium ambients. Each gas demonstrated a unique breakdown signature. Further, the sensor was tested with gaseous mixtures. The sensor exhibited good long-term stability and had comparable performance to other reported CNT-based ionization sensors in literature, which use high-temperature vapor deposition methods to grow CNTs. The sensor notably allowed for lower ionization voltages due to its reduced ionization gap size

Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits

In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption